1. Field of the Invention
The present invention relates to an electrostatic discharge protection element. In particular, the present invention relates to the electrostatic discharge protection element that is provided in a semiconductor integrated circuit in order to protect the semiconductor integrated circuit from breakdown due to entrance of static electricity into the semiconductor integrated circuit from the outside or due to the phenomenon of electrostatic release to the outside from the charged semiconductor integrated circuit.
2. Description of the Background Art
The phenomena of charge of, or release of, static electricity, which are considered to be a problem when handling a semiconductor integrated circuit, are phenomena wherein the semiconductor integrated circuit becomes electrically charged when static electricity flows in from a charged mechanical apparatus or from a human being at the time the semiconductor integrated circuit is handled by the mechanical apparatus or human being and are phenomena wherein the semiconductor integrated circuit discharges static electricity to an external conductor after the semiconductor integrated circuit itself has become electrically charged due to vibration, friction, or the like, which occur at the time of conveyance. Static electricity is instantly charged to the semiconductor integrated circuit or is discharged from the semiconductor integrated circuit as a result of such electrostatic phenomena and, therefore, an excessive current flows through the semiconductor integrated circuit. Thus, an excessive voltage corresponding to this excessive current is applied to an internal circuit thereof. Therefore, junction breakdown, insulating film breakdown, wire blowout, or the like, occur inside the semiconductor integrated circuit and there is a risk wherein the semiconductor integrated circuit may be destroyed.
In general, an electrostatic discharge protection element is provided between an external terminal of the semiconductor integrated circuit and the internal circuit thereof in order to protect the semiconductor integrated circuit from breakdown due to static electricity and this becomes a detour for static electricity. Such the electrostatic discharge protection element is formed using a manufacturing process for forming the semiconductor integrated circuit. Here, it is desirable to form such the element without adding a specific manufacturing process to the manufacturing process for forming the semiconductor integrated circuit so that the manufacturing cost thereof is not increased.
The electrostatic discharge protection element has a structure wherein a current limiting element and a voltage clamp element are appropriately combined. A current limiting element is an element for limiting current that transiently flows through the semiconductor integrated circuit and a diffused resistor, a polycrystal silicon resistor, and the like, can be cited as examples thereof. On the other hand, a voltage clamp element is an element for suppressing the voltage applied to the internal circuit and a diode, a bipolar transistor, a MOS transistor, a thyristor, and the like, can be cited as examples thereof.
In particular, the thyristor has an advantage as the voltage clamp element that allows excessive current to flow. However, a trigger voltage for converting the thyristor, which is used for example with a power apparatus, to the ON-state so that current starts flowing is a high voltage and, therefore, the possibility of breakdown of the semiconductor integrated circuit before the thyristor turns on is very high. Therefore, it is necessary to reduce the trigger voltage Vtr.
FIG. 7 shows a schematic diagram of the I-V characteristics required for an SCR element, as the electrostatic discharge protection element, at the time of application of an electrostatic surge. In the figure the voltage wherein the SCR element starts avalanche breakdown is denoted as Vtr, the first breakdown voltage is denoted as Vt1 and the holding voltage is denoted as VH. Here, the electrostatic discharge protection element (i) must have a withstand voltage (BVox) of an oxide film at the time of application of a surge that does not exceed first breakdown voltage (Vt1) in order to protect the gate oxide film of the internal circuit from breakdown due to electrostatic surge and (ii) must have holding voltage (VH) exceed the maximum operational voltage (Vddmax) of the internal circuit in order to prevent the latching up of the circuit at the time of conventional operation.
A technology described in, for example, U.S. Pat. No. 6,524,893 is cited as the above described prior art and this is described below in reference to FIGS. 4(a) and 4(b). FIG. 4(a) shows a schematic cross sectional view and FIG. 4(b) shows an equivalent circuit diagram of FIG. 4(a). This technology relates to the electrostatic discharge protection element using the thyristor wherein reduction in the trigger voltage is achieved. The thyristor described in this gazette includes a trigger diode for triggering the thyristor into the ON-state at a low voltage. This trigger diode is provided with an n-type cathode high concentration impurity region 6, a p-type anode high concentration impurity region 4, a silicide layer formed on the surface of this n-type cathode high concentration impurity region 6, a silicide layer formed on the surface of this p-type anode high concentration impurity region 4 and a means (element isolation region) for electrically isolating the region 6 from the region 4 and, thereby, this trigger diode can be manufactured without adding any special processes, in particular a photography process, to the manufacturing process for the semiconductor integrated circuit, which includes the step of the formation of silicide, and without increase in the cost of manufacture. In FIG. 4(a), a p-type silicon substrate is denoted as 1, a p-type well is denoted as 1′, an n-type well is denoted as 2, a shallow trench isolation (STI) is denoted as 3, an n-type anode high concentration impurity region is denoted as 5, a p-type cathode high concentration impurity region is denoted as 7, a p-type high concentration impurity region is denoted as 8, an n-type high concentration impurity region is denotes as 9, silicide layers are denoted as 10a to 10f and 11, sidewalls are denoted as 12, a gate oxide film is denoted as 13, a gate polysilicon is denoted as 14, an oxide film is denoted as 15, contacts are denoted as 16a to 16d, metal wires are denoted as 17 and 18, a trigger diode is denoted as D, the resistance of the n well is denoted as Rnw, the resistance of the p well is denoted as Rpw, a first transistor is denoted as Tr1 and a second transistor is denoted as Tr2.
When modern manufacturing processes are introduced in order to reduce the minimum processing dimensions, however, the power supply voltage for the operation of the semiconductor integrated circuit is lowered and short channel effects in the transistors easily occur. The impurity concentrations of the n wells and p well must be enhanced or the film thickness of the gate insulator films must be reduced in order to prevent this and, as a result, the insulation breakdown voltage of the gate insulating films is reduced.
Thus, enhancement in the concentration of the impurities in the two types of wells, together with the miniaturization of the transistors, leads to reduction in n well resistance Rnw and in p well resistance Rpw and, therefore, voltage Vtr, according to which the trigger diode for converting the thyristor to the ON-state starts operating, is reduced in the thyristor, which has a conventional structure.
The first breakdown voltage Vt1 determined by the amount of current flowing through the trigger diode, however, is uniquely determined in accordance with the well concentration and, therefore, it is difficult to adjust this first breakdown voltage Vt1.
Accordingly, it is desirable to make the first breakdown voltage Vt1, according to which the thyristor is converted to the ON-state, adjustable so that the thyristor can be manufactured according to any type of process as well as to lower the trigger voltage Vtr. Furthermore, it is also desirable to suppress unstable operation of the thyristor that occurs in the case wherein the gate potential of the trigger diode is in the floating condition.